Sometimes you wonder why a certain configuration on the PSoC4 Pioneer kit is not working like you expected. It might be that you are using a pin that is connected somewhere on the board… therefore, see the PSoC4 Pioneer Kit Pinout below. The list comes with absolutely no warranty!
| Pin | Pioneer Kit Function | Pioneer Kit Connection | Pin accessible | Internal connection |
| P0_0 | y | COMP1:Inp, SCB0:SPI_ssel[1] | ||
| P0_1 | Shield Setting | Shield | y | COMP1:Inp, SCB0:SPI_ssel[2] |
| P0_2 | RGB LED G | RGB LED G | y | COMP2:Inp, SCB0:SPI_ssel[3] |
| P0_3 | RGB LED B | RGB LED B | y | COMP2:inn |
| P0_4 | y | SCB1:uart_rx, SCB1:i2c_scl, SCB1:spi_mosi | ||
| P0_5 | y | SCB1:uart_tx, SCB1:i2c_sda, SCB1:spi_miso | ||
| P0_6 | y | SRSS:ext_clk, SCB1:spi_clk | ||
| P0_7 | User Button | SW2, Pull down | y | SRSS:wakeup, SCB1:spi_ssel[0] |
| P1_0 | y | OA0:vplis, TCPWM2:line_out | ||
| P1_1 | CapSense Slider | Capsense Pad | y | OA0:vminus, TCPWM2:line_out_compl |
| P1_2 | CapSense Slider | Capsense Pad | y | OA0:vout_10x, TCPWM3_line_out |
| P1_3 | CapSense Slider | Capsense Pad | y | OA1:vout_10x, TCPWM3_line_out_compl |
| P1_4 | CapSense Slider | Capsense Pad | y | OA1:vminus |
| P1_5 | CapSense Slider | Capsense Pad | y | OA1_vplus |
| P1_6 | RGB LED R | RGB LED R | PA0_vplus_alt | |
| P1_7 | SAR bypass | 1µF Cap | y | OA1:vplus_alt, SAR_ext_vref |
| P2_0 | y | SARMUX:in[0] | ||
| P2_1 | y | SARMUX:in[1] | ||
| P2_2 | y | SARMUX:in[2] | ||
| P2_3 | y | SARMUX:in[3] | ||
| P2_4 | y | SARMUX:in[4], TCPWM0:line_out | ||
| P2_5 | y | SARMUX:in[5], TCPW0:line_out_compl | ||
| P2_6 | y | SARMUX:in[6], TCPWM1:line_out | ||
| P2_7 | y | SARMUX:in[7], TCPWM1:line_out_compl | ||
| P3_0 | y | TCPWM0:line_out, SCB1:uart_rx, SCB1:i2c_scl, SCB1:spi_mosi | ||
| P3_1 | y | TCPWM0:line_out_compl, SCB1:uart_tx, SCB1:i2c_sda, SCB1:spi_miso | ||
| P3_2 | SWDIO | PSoC5LP | ||
| P3_3 | SWDCLK | PSoC5LP | ||
| P3_4 | y | TCPWM2:line_out, SCB1:spi_ssel[1] | ||
| P3_5 | y | TCPWM2:line_out_compl, SCB1:spi_ssel[2] | ||
| P3_6 | y | TCPWM3:line_out, SCB1:spu_ssel[3] | ||
| P3_7 | y | TCPWM3:line_out_compl | ||
| P4_0 | y | SCB0:uart_rx, SCB0:i2c_scl, SCB0:spi_mosi | ||
| P4_1 | y | SCB0:uart_tx, SCB0:i2c_sda, SCB0:spi_miso | ||
| P4_2 | Capsense Tuning Circuit | Shunt parallel 2.2nF Cap | CSD:c_mod, SCB0:spi_clk | |
| P4_3 | Sh_tank | 10nF Cap | CSD:c_sh_tank, SCB0:spi_ssel[0] |